An open GNSS receiver platform architecture
Custom GNSS platform
The third task was to develop a custom designed circuit board and then port the GPS Architect software to it. The board is shown in fi gure 4, it has an Altera CycloneII FPGA device and a Zarlink 2015 RF frontend. For IO there is an Ethernet port, two RS232 serial ports and a JTAG programming / debugging port. There is sram and flash memory as well as a confi guration controller and serial fl ash. There are expansion headers, a real time clock, a three axis accelerometer, leds, switches and sma connectors.
The board was designed for very low noise to keep interference with the sensitive RF front end down. It can be seen in fi gure 5 that the IF output of the 2015 RF chip is free from interference spikes.
A single channel baseband processor has been built on this board to test the correlation functions and tune the tracking loops. Correlation peaks have been obtained from signals injected from a Spirent GPS simulator. Figure 6 shows a correlation plot, on the xaxis is the code delay (in half-chips) over two carrier doppler bins, and on the y-axis is the correlation power.
Shortly, we will fi nish working on the tracking loops and then the GPS Architect is pretty much ready to run on the custom GNSS board. There
The infl exibility of the RF front end was eluded to earlier in this article. The custom board has only an L1 (1575MHz) front end. Due to passband fi ltering and available chips, it is diffi cult to make a front end that covers more bands. Our solution was to provide a header and some sma
clock connectors to allow a daughter board to be attached later for access to other signals. Daughter boards can be built to suite the Galileo and new GPS signals once the RF chips are available.
Due to the confi gurable nature of FPGA’s, there are many possibilities for research using this platform including:
• Baseband signal processing design: improved tracking in weak signal and multi-path environments.
• Investigating new signals.
• DSP search engine: for signal acquisition and tracking, particularly for weak signals.
• Develop the GPS Architect software for better performance or specifi c functionality.
• Replace the GPS Architect.
• Raw data collection and packaging for PC based soft receiver processing.
• Signal interference (jamming) detection.
• Ultra-tight INS integration.
The project is heading towards completion. We have the FPGA GNSS circuit board running a single channel baseband processor, tracking a GPS satellite. We have the GPS Architect software ready to run on the NiosII processor. We hope to complete testing and report our results in early 2006. We hope that our work will then be of value to the GNSS research community.
FCC (2004) Wireless Enhanced
WAAS (2004) Wide Area
Altera (2004) Stratix Device –
EGNOS (2004) European
SBAS (2004) Satellite Base
GLONASS (2004) GLONASS
Canalys (2004) EMEA mobile GPS
Galileo (2004) Galileo, European
Petrovski I (2003) QZSS – Japan’s
Zarlink (2001) GP2021 GPS
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